TransEDA Tools Speed Verification Process for Paxonet Communications' New Optical Networking Products

LOS GATOS, Calif. - April 15, 2002 - TransEDA® PLC, the leader in ready-to-use verification solutions for electronic designs, announced that Paxonet Communications standardized on TransEDA's VN-Cover™ coverage analysis solution as part of its verification methodology for its new optical networking products. Paxonet is a fabless application specific standard product (ASSP) company that provides solutions for next generation optical networks.

"With VN-Cover, we can really increase our confidence that our designs are fully verified," said Simon Matthews, chief engineer, Paxonet Communications. "Although we used the basic coverage analysis capabilities provided with our simulator, we found it insufficient for rapid improvement of our coverage. We typically shoot for 95 percent comprehensive coverage in our designs, and are able to meet close to 100 percent for statement and branch. TransEDA goes beyond this to provide a complete set of coverage metrics in an easy-to-use environment that helps us speed coverage closure and design release."

Paxonet recently used TransEDA's VN-Cover to verify its Chopper product-an integrated, single-chip solution for performing classification and policing of packets and cells in a network. With two million gates, the product required extensive test benches to be written. The company also successfully used the product for validation of test benches in its 10G Ethernet MAC core. Paxonet used VN-Cover during simulations run at the module level of the designs rather than the chip level. The company finds this methodology speeds the overall verification process. IP validated at the module level can also be reused in future designs, cutting design time for those projects.

"Using TransEDA's products on our new 10G MAC core and Chopper product proved to be a good decision, as we found a few bugs we had not previously discovered," said Pramod Phadke, general manager - engineering, Paxonet. "VN-Cover gives us an objective way to validate our test scripts-a process that was previously largely manual. In order to gain full confidence in our verification effort, we had to spend many more man-hours. Because we use VN-Cover at the module level, we are able to detect and correct bugs up front. During this process, VN-Cover helps us especially in identifying corner cases that we may have overlooked in our initial test scripts. The end result is faster simulation, higher productivity, and pre-verified IP that speeds the completion of future designs."

About TransEDA
TransEDA PLC (symbol TRA on the Alternative Investment Market in London) develops and markets ready-to-use verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs. The company's verification IP library includes models and properties for advanced microprocessors and bus interfaces. TransEDA's design verification software performs dynamic property checking, application-specific test automation, configurable HDL checking, finite state machine (FSM) and code coverage analysis, and test suite analysis. TransEDA's tier-1 list of customers includes 18 of the world's top 20 semiconductor vendors. For more information, visit www.transeda.com or contact TransEDA at 983 University Avenue, Building C, Los Gatos, California 95032 U.S.A., telephone (408) 335-1300, fax (408) 335-1319, email info@transeda.com.

Note: TransEDA and Verification Navigator are registered trademarks and VN-Cover is a trademark of TransEDA PLC. All other trademarks are properties of their respective holders.

MEDIA CONTACTS:

In North America, Asia, and Japan:
TransEDA
Tom Borgstrom
408.335.1303
tom.borgstrom@transeda.com

Armstrong Kendall, Inc.
Jen Bernier
408.975.9863
jen@akipr.com

In the U.K. and Europe:
PentaCom
Sharon Graves
+44 1242 525205
sharon.graves@pentacomagency.com

Beattie Financial
Annmarie Wilkinson
+44 020 7398 3300
annmarie.wilkinson@beattiefinancial.com